Decimal floating-point platform support with the binary integer decimal encoding

Decimal numbers permeate our global economy in commerce, trade, banking, and business, with the proliferation of monetary transactions and increasing demand for financial computations. However, modern computers perform binary arithmetic, which has flaws in representing and rounding decimal numbers. The problem of generating correct decimal results using binary circuits is not a new one, but it has received renewed interest in recent years. Because the demand for decimal floating-point arithmetic is predicted to grow, the approved IEEE 754-2008 Standard for Floating-Point Arithmetic (IEEE 754-2008) includes specifications for decimal floating-point (DFP) arithmetic. This dissertation provides fundamental knowledge about and an improved understanding of DFP arithmetic. One of the DFP encodings specified in IEEE 754-2008 represents the significand as a binary integer and is commonly referred to as the binary integer decimal (BID) encoding. This dissertation answers important questions about BID hardware issues. In particular, it provides the first hardware-based algorithms and hardware designs for this encoding and examines the designs' potential to reuse high-speed binary arithmetic circuits. This dissertation also provides insights into the strengths and weaknesses of solutions that support the BID encoding. The BID-based DFP hardware designs in this dissertation include rounders, an adder/subtractor, and a multiplier that are compliant with IEEE 754-2008. Each of these units is the first of its kind to provide hardware support for BID-encoded operands. This dissertation also presents the first designs for a BID multifunction unit and a combined BID and binary floating-point multiplier. The presented BID hardware solutions are evaluated in terms of area, delay, and latency—estimates that may be valuable in making design decisions for DFP support in future computer systems. As of May 2009, only one major computer manufacturer currently offers commercial DFP hardware solutions, and demand for DFP is currently concentrated in the server and mainframe markets. However, other microprocessor manufacturers may soon include hardware support, and demand for DFP arithmetic is predicted to expand into other markets. As research yields improved DFP hardware designs, handheld, mobile, and desktop markets may also include DFP support. This dissertation is one step towards realizing that future.