Design of Energy Aware Data ProcessingArchitecture for Wireless Sensor Nodes

Wireless Sensor Networks (WSN) has become a very significant enabling technology in civil, military, radio communication and medical applications for collecting and processing of complex environmental data. Radio communication has highest energy consumption in wireless sensor nodes. Sensor nodes are battery driven and have lifetime on the order of months to years. Hence, energy consumption is the important factor in determining sensor nodes lifetime. To reduce the number of processing elements in sensor nodes, folded tree architecture is used. Here proposing, DVFS (Dynamic Voltage and Frequency Scaling) algorithm is used along with folded tree architecture to reduce power and to improve performance of sensor nodes. As wireless nodes are expensive to buy replace it’s important to increase life time of nodes in order to increase life time of nodes we are going to use folded tree architecture.to reduce power in wireless sensor node by using reused technology of PES(processing elements).in previous works they used 2N number of PES. In our project we used half amount of PE. Software used xilinix, proposed to work –combination of energy saving algorithm and hardware decreases power and increases node life time.

[1]  Gu-Yeon Wei,et al.  Survey of Hardware Systems for Wireless Sensor Networks , 2008, J. Low Power Electron..

[2]  Gu-Yeon Wei,et al.  An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS , 2009, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[3]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[4]  Andreas Willig,et al.  Protocols and Architectures for Wireless Sensor Networks , 2005 .

[5]  Wim Dehaene,et al.  Design of a low-energy data processing architecture for WSN nodes , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[6]  Frederic T. Chong,et al.  Exploring the Processor and ISA Design for Wireless Sensor Network Applications , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[7]  Rajit Manohar,et al.  BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[8]  Rajit Manohar,et al.  An ultra low-power processor for sensor networks , 2004, ASPLOS XI.

[9]  Jesper Larsson Träff,et al.  Parallel Prefix (Scan) Algorithms for MPI , 2006, PVM/MPI.