Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially Stressed nMOSFETs

We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mum, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is also validated.

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