Partitioning of DSP tasks to Kahn network

Recently the number of digital signal processing (DSP) applications is increasingly growing. Modern extensive application domains are audio processing, digital communications, speech recognition, spatial positioning, etc. One essential feature of the mentioned applications is hard real time processing of real world signals. Occasionally chosen processing architecture may not satisfy processing time and hardware resource restrictions set by the application. Therefore, selection of application-dedicated architecture is needed. Architecture selection presents design-space-exploration task. This task in general is hardly solvable as there exist a lot of design alternatives to explore: number of different DSP algorithms, processing elements, design techniques and tools. Usual way to make architecture selection more effective is to build design methodology. The methodology should constrain in some way design space and use systematic approaches to solve problematic design aspects. A lot of different methodologies for the DSP architecture design have been proposed. Recent methodologies mainly are dedicated for the evaluation of DSP architectures from the application system level description. Most typical ones were proposed in the projects Ptolemy [11], Match [10], also the SPADE methodology [7], etc. These methodologies deals mainly with application and architecture models, however, they provide less attention to mapping these application model into real-time hardware prototype. This paper proposes a methodology for mapping the DSP task into different processing architectures. This methodology includes task specification, algorithm analysis, functional partitioning and mapping the task presented by Kahn network into the hardware-prototyped DSP architecture. The mapping process is illustrated with the multi-channel correlation processing task that is common in such applications as various measurements, sonar and radar positioning [1,4].