Simulation of large asynchronous logic circuits using an ambiguous gate model

Digital logic simulation is the process whereby the action of a logic circuit due to a specified input is predicted based upon some model of the circuit. Logic simulation is becoming increasingly necessary as larger and more complex computers are built. Because of the cost of building hardware it is not wise to commit a circuit design to manufacture without first verifying the operation of the circuit by simulation. This is true even for large computers (say 50,000 gates) where simulation will eliminate many logic errors and may save construction of a prototype model. Simulation may be used to predict the output of the circuit due to specified faults as well as to predict the output of the good (fault free) circuit. A dictionary is generally compiled of the output of the circuit in the presence of known faults. By comparing the actual (perhaps faulty) circuit output to the correct output, it is possible to detect and diagnose a fault in the circuit.