Novel Design of one digit high speed Carry select BCD Subtractor using Reversible logic gates

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This work proposes subtraction of decimal numbers using Carry Select logic to minimize computation delay while reducing power dissipation. The design makes use of existing reversible fault tolerant gates such as Fredkin, Peres and MKG gates. The research also proposes a new gate for computation of Nine's complement result for subtraction. It is being tried to design the BCD subtractor optimal in terms of number of reversible gates and garbage outputs