Silicon hybrid wafer-scale package technology

A wafer-scale packaging technology is discussed. Pretested IC chips are mounted in holes etched through silicon wafers. Chips are interconnected via the wafer using standard multilevel metallization processes. The packaging technology has the potential to provide the flexibility of hybrid techniques with the reliability and density of monolithic fabrication.

[1]  J. Prokop,et al.  Chip Carriers as a Means for High-Density Packaging , 1978 .

[2]  T.E. Mangir,et al.  Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI , 1984, Proceedings of the IEEE.

[3]  K. Bean,et al.  Anisotropic etching of silicon , 1978, IEEE Transactions on Electron Devices.

[4]  J. Greene,et al.  Area and Delay Penalties in Restructurable Wafer-Scale Arrays , 1983 .

[5]  Algirdas Avizienis,et al.  Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs , 1982, IEEE Transactions on Computers.

[6]  Melvin A. Breuer,et al.  On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays , 1984, IEEE Transactions on Computers.

[7]  Victor M. Bermudez,et al.  Ellipsometric Study of Orientation‐Dependent Etching of Silicon in Aqueous KOH , 1985 .

[8]  J. W. Lathrop,et al.  A discretionary wiring system as the interface between design automation and semiconductor array manufacture , 1967 .

[10]  R. Dunn,et al.  Active memory design using discretionary wiring for LSI , 1967 .

[12]  K. Mukai,et al.  Planar multilevel interconnection technology employing a polyimide , 1978 .

[13]  N. Kanopoulos,et al.  Yield improvement of wafer-scale integrated systolic structures via redundancy , 1983 .

[14]  J. Raffel,et al.  Laser programmed vias for restructurable VLSI , 1980, 1980 International Electron Devices Meeting.

[16]  A. Wilson.  Polyimide insulators for multilevel interconnections , 1981 .

[17]  R.C. Aubusson,et al.  Wafer-scale integration-a fault-tolerant procedure , 1978, IEEE Journal of Solid-State Circuits.

[18]  Richard C. Jaeger,et al.  Hybrid silicon wafer-scale packaging technology , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  C. Huang,et al.  Silicon-On-Silicon Packaging , 1984 .

[20]  Donald F. Calhoun.  The pad relocation technique for interconnecting LSI arrays of imperfect yield , 1969, AFIPS '69 (Fall).

[21]  Kye Sherrick Hedlund.  Wafer scale integration of configurable, highly parallel processors , 1982 .