Implementation of a Fine-Grained Parallel Full Pipeline Schnorr–Euchner Sphere Decoder Algorithm Accelerator on Field-Programmable Gate Array

A new parallel full pipeline accelerator implemented on field-programmable gate array (FPGA) for the Schnorr–Euchner sphere decoding (SE–SD) algorithm is presented in this paper. We firstly transform the serial SE–SD algorithm into a parallel one. Afterwards, we use multiple processing elements (PEs) to deal with the workload (particularly for tree searching in the SE–SD algorithm) in parallel. Each separated SE–SD search workload is divided averagely. Each PE searches a sub-tree by using a multilevel pipeline to increase the data throughput, and the whole system obtains a batch of different input data chronologically. We select the number of PEs to distribute our system according to the hardware platform by using a distribution unit. We’ve successfully placed four PEs in an accelerator and eight accelerators in a single FPGA (XC6VLX240T). The system obtains remarkable benefit in changing the accelerate mode, including latency- and throughput-prior modes.