MappingArbitrary LogicFunctions intoSynchronous EmbeddedMemoriesForAreaReduction on FPGAs

Thisworkdescribes a new mappingtechnique, RAM-MAP, thatidentifies partsofcircuits that can beefficiently mappedintothesynchronous embeddedmemoriesfoundon field programmable gatearrays (FPGAs).Previous techniquesdeveloped formappingintoasynchronous embeddedmemories cannotbeusedbecause modernFPGAsdo nothaveasynchronous embeddedmemories. Aftertechnology mapping, an area-prediction costfunction isused toguidetheselection oflogic cones tobeplaced inembeddedmemories.Extralogic isaddedtocompensate formissing asynchronous functionality on thesynchronous memories. Experiments conducted on Altera's Stratix devicefamily indicate thatthisembedded memory mapping technique can provide an average area reduction of6.2% andup to32.5%on a large setofindustrial designs. A smallarchitecture changethatincreases thesizeofthe FPGA fabric by0.05%can increase theaverage area reduction to14.1%andup to59.1%on thesame design set.