Next-generation microvia and global wiring technologies for SOP

As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-/spl mu/m area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 /spl mu/m diameter and lines and spaces of 25 /spl mu/m. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for micro via wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 /spl mu/m and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.

[1]  K. Segawa.  Build-up PWB with laser-processed via holes VIL , 1998 .

[2]  Robert A. Shick,et al.  Crosslinking and decomposition reactions of epoxide functionalized polynorbornene. Part I. FTIR and thermogravimetric analysis , 2003 .

[3]  S. Bhattacharya,et al.  Selection and evaluation of materials for future system-on-package (SOP) substrate , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[4]  Yutaka Tsukada,et al.  Surface laminar circuit packaging , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[5]  Shih-Chin Lee,et al.  Electroless deposition of Cu thin films with CuCl2-HNO3 based chemistry. I. Chemical formulation and reaction mechanisms , 2001 .

[6]  Tadashi Nakamura,et al.  The progress of the ALIVH substrate , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[7]  P. Kohl,et al.  Porous Methylsilsesquioxane for Low-k Dielectric Applications , 2001 .

[8]  S. Nakahara,et al.  The Effect of Grain Size on Ductility and Impurity Content of Electroless Copper Deposits , 1989 .

[9]  C. Iwakura,et al.  Kinetics of Electroless Copper Plating and Mechanical Properties of Deposits , 1992 .

[10]  D. Y. Yoon,et al.  Templating Nanopores Into Poly(MethylSilsesquioxane): New Lowdielectric Coatings Suitable for MicroElectronic Applications , 1998 .

[11]  P. Kohl,et al.  Variable frequency microwave curing of photosensitive polyimides , 2001 .

[12]  Fuhan Liu,et al.  The role of stiff base substrates in warpage reduction for future high-density-wiring requirements , 2002, 2002 Proceedings. 8th International Advanced Packaging Materials Symposium (Cat. No.02TH8617).

[13]  Fuhan Liu,et al.  Fabrication of ultra-fine line circuits on PWB substrates , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[14]  Rao Tummala,et al.  Ultra-HDI with low cost photo-imageable polymers , 2001, Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (IEEE Cat. No.01TH8562).

[15]  J. Collins,et al.  The redox properties of active sites and the importance of the latter in electrocatalysis at copper in base , 1998 .

[16]  P. Wayner,et al.  Fabrication and Characterization of Spin-On Silica Xerogel Films , 1998 .

[17]  Fuhan Liu,et al.  A novel technology for stacking microvias on printed wiring board , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[18]  W. Xu,et al.  Electroless copper plating using hypophosphite as reducing agent , 1997 .

[19]  Motoo Asai.  New Packaging Substrate Technology,Ibss (Interpenetrating Polymer Network Build Up Structure System) , 1996 .

[20]  Schmidt,et al.  Modern interconnect solutions for miniaturized medical electronic devices , 2000 .

[21]  Ker-Ming Chen,et al.  Mechanism of Hypophosphite‐Reduced Electroless Copper Plating , 1989 .

[22]  P. Kohl,et al.  Photosensitive polynorbornene based dielectric. I. Structure–property relationships , 2004 .

[23]  Y. Fukuoka,et al.  New high Density Substrates with buried bump interconnection technology (B2it ) : Design features of electrical and thermal performance with the actual applications , 1998 .

[24]  P. Kohl,et al.  Variable frequency microwave curing of 3,3', 4,4'- biphenyltetracarboxylic acid dianhydride/P-phenylenediamine (BPDA/PPD) , 2000 .

[25]  S. Yen,et al.  Effects of additives and chelating agents on electroless copper plating , 2001 .

[26]  Satoru Kuramochi,et al.  High-density packaging technologies on silicon substrates , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[27]  P. Kohl,et al.  Photosensitive polynorbornene based dielectric. II. Sensitivity and spatial resolution , 2004 .

[28]  P. Kohl,et al.  Variable‐frequency microwave curing of benzocyclobutene , 2002 .