An open-loop clock generator for fast frequency scaling in 65nm CMOS technology

This paper presents an open-loop clock generator circuit for MPSoC applications. Based on an 8-phase reference clock a wide range of output frequencies with 50% duty cycle can be generated using a reverse phase switching technique. An optimized phase multiplexer enables operation at high input frequencies. Control signal synchronization allows the output frequency to be changed arbitrarily within a single clock cycle. The circuit has been implemented in 65nm CMOS technology. When operating at 2GHz input frequency, clocks from 83MHz to 666MHz can be generated with a typical power consumption between 0.6mW and 1.6mW.

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