Design for debug: catching design errors in digital chips
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[1] Don Douglas Josephson,et al. Debug methodology for the McKinley processor , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[2] J.L. van Meerbergen,et al. Heterogeneous multiprocessor for the management of real-time video and graphics streams , 2000, IEEE Journal of Solid-State Circuits.
[3] Santanu Dutta,et al. Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..
[4] Bart Vermeulen,et al. Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[5] Bart Vermeulen,et al. Silicon debug: scan chains alone are not enough , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[6] Jos van Beers,et al. Test features of a core-based co-processor array for video applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[7] Derek Feltham,et al. Pentium(R) Pro processor design for test and debug , 1997, Proceedings International Test Conference 1997.
[8] Sridhar Narayanan,et al. Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[9] Hong Hao,et al. Clock controller design in SuperSPARC II microprocessor , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[10] Derek Feltham,et al. Pentium Pro Processor Design for Test and Debug , 1998, IEEE Des. Test Comput..
[11] Alfred L. Crouch,et al. Testability features of the MC68060 microprocessor , 1994, Proceedings., International Test Conference.