Self-aligned double patterning (SADP) layout decomposition

Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.

[1]  Huixiong Dai,et al.  Implementing self-aligned double patterning on non-gridded design layouts , 2009, Advanced Lithography.

[2]  Vincent Wiaux,et al.  Application challenges with double patterning technology (DPT) beyond 45 nm , 2006, SPIE Photomask Technology.

[3]  Shiro Kusumoto,et al.  Double patterning process with freezing technique , 2009, Advanced Lithography.

[4]  Vincent Wiaux,et al.  Split and design guidelines for double patterning , 2008, SPIE Advanced Lithography.

[5]  Patrick Jaenen,et al.  Pitch doubling through dual-patterning lithography challenges in integration and litho budgets , 2007, SPIE Advanced Lithography.

[6]  Vincent Wiaux,et al.  Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows , 2009 .

[7]  Yi-Shiang Chang,et al.  Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond , 2009, Advanced Lithography.

[8]  Xin Gao,et al.  Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[9]  David Z. Pan,et al.  Double patterning technology friendly detailed routing , 2008, ICCAD 2008.

[10]  Vincent Wiaux,et al.  Double pattern EDA solutions for 32nm HP and beyond , 2007, SPIE Advanced Lithography.

[11]  Warren Montgomery,et al.  22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP) , 2008, SPIE Advanced Lithography.

[12]  Andrew B. Kahng,et al.  Layout Decomposition Approaches for Double Patterning Lithography , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Vincent Wiaux,et al.  Double patterning design split implementation and validation for the 32nm node , 2007, SPIE Advanced Lithography.

[14]  Kun Yuan,et al.  Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization , 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..