The new Low-Level Radio Frequency (LLRF) control system for linear accelerator at Legnaro National Laboratories (LNL) of INFN is presently being commissioned. A digital Radio Frequency (RF) controller was implemented. Its goal is to stabilize the amplitude, the phase and the frequency of the superconducting cavities of the Linac. The resonance frequency of the low beta cavities is 80 MHz, while medium and high beta cavities resonate at 160 MHz. Each RF controller controls at the same time eight different cavities. The hardware complexity of the RF controller (RF IOC) is reduced by adopting direct RF sampling and the RF to baseband conversion method. The main hardware components are RF ADCs for the direct undersampling of the signals picked up from cavities, a Xilinx Kintek 7 FPGA for the signal processing and DACs for driving the power amplifiers and hence the cavities. In the RF IOC the serial communication between FPGA and ADCs and between FPGA and DACs is based on JESD204b standard. An RF front-end board (RFFE) is placed between cavities and the RF IOC. This is used to adapt the power level of the RF signal from the cavities to the ADCs and from the DACs to the power amplifiers. This paper addresses the LLRF control system focusing on the hardware design of the RF IOC and RFFE boards and on the first test results carried out with the new controller. INTRODUCTION The superconducting linear accelerator ALPI [1] requires a significant RF field stability in phase, amplitude and frequency to ensure the best energy gain of the accelerated beam. The resonance frequency of a first group of ALPI cavities is 80 MHz, while that of a second group is 160 MHz. The cavities act as filters, with an high quality factor. In order to keep the RF field stable in the cavities, amplitude and phase have to be controlled to compensate the impact of microphonic perturbations. RF CONTROLLER In order to improve the stability of the RF field in the cavities a new RF control system has been developed [2]. The new digital RF controller system has been designed exploiting the performances of commercial components like RF ADCs, FPGA and DACs. It is based on direct sampling of RF signal and digital signal processing with FPGA. This allows a greater flexibility in programming and diagnostic ∗ stefano.pavinato@lnl.infn.it capabilities, since it is possible to monitor many signals during the processing of the data inside the FPGA, like amplitude and phase of the RF fields in cavities. CHIPSCOPE XILINX LABTOOLS EPICS IOC PC ... ... ... .. ... ... PLL PLL ADC ADC DAC DAC FPGA VCXO VCXO JTAG