Artificial neural-network model-based observers

Describes a pseudorandom testing scheme for fault diagnosis of analog integrated circuits. The goal is to implement a BIST technique with both a built-in pattern generator and a response analyzer for fault diagnosis. We have chosen a diagnostic framework for the analog ICs using a pseudorandom noise generator as the test-pattern generator and a model-based observer to detect and diagnose faults. The observer is implemented through a multilayer feedforward ANN trained with a back-error propagation (BEP) algorithm. Both the test-pattern generator and the model-based observer proposed in this article can be implemented either on- or offline depending on the need of the application and silicon area overhead.

[1]  D. O. Pederson,et al.  A computer-aided evaluation of the 741 amplifier , 1971 .

[2]  B. Kaminska,et al.  An integrated approach for analog circuit testing with a minimum number of detected parameters , 1994, Proceedings., International Test Conference.

[3]  Rolf Isermann,et al.  Process fault detection based on modeling and estimation methods - A survey , 1984, Autom..

[4]  Mahmoud Al-Qutayri,et al.  Go/no-go testing of analogue macros , 1992 .

[5]  José Luis Huertas,et al.  Analog and mixed-signal benchmark circuits-first release , 1997, Proceedings International Test Conference 1997.

[6]  Chin-Long Wey,et al.  Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data , 1992 .

[7]  A. P. Dorey,et al.  Testing analogue circuits by power supply voltage control , 1994 .

[8]  Abhijit Chatterjee,et al.  Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[9]  B. W. Jervis,et al.  Diagnosis of multifaults in analogue circuits using multilayer perceptrons , 1997 .

[10]  A. P. Dorey,et al.  A design-for-test structure for optimising analogue and mixed signal IC test , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[11]  Shambhu Upadhyaya,et al.  Linear circuit fault diagnosis using neuromorphic analyzers , 1997 .

[12]  Rolf Isermann,et al.  Process Fault Detection Based on Modeling and Estimation Methods , 1982 .

[13]  L. T. Wurtz.  Built-in self-test structure for mixed-mode circuits , 1993 .

[14]  Mark R. DeYong,et al.  i/sub DD/ pulse response testing: a unified approach to testing digital and analogue ICs , 1993 .

[15]  Paul M. Frank,et al.  Fault diagnosis in dynamic systems using analytical and knowledge-based redundancy: A survey and some new results , 1990, Autom..

[16]  Vladimir Kolarik,et al.  A design-for-test technique for switched-capacitor filters , 1994, Proceedings of IEEE VLSI Test Symposium.

[17]  Alkis A. Hatzopoulos,et al.  Supply current testing in linear bipolar ICs , 1994 .

[18]  Alok Barua,et al.  A pseudo-random testing scheme for analog integrated circuits using artificial neural network model-based observers , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..