Test challenges in nanometric CMOS technologies

Abstract The current trends in decreasing the minimum feature sizes in CMOS technologies are producing new failure mechanisms for which the classical test methods become inefficient. This situation causes a growing concern in the design and test communities due to the fact that the advances in integration advance faster than the ability of test specialists in providing the required strategies to test the new circuits. If the current levels of reliability are to be maintained new paradigms to guarantee the quality levels of the future megatransitor chips will be required. In this paper, after reviewing the technology trends in CMOS technologies, the emerging failure mechanisms of these technologies are analyzed. The challenges facing testing in nanometric technologies are explored in terms of voltage test difficulties as well as current test (IDDQ) problems and solutions.

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