A transformation-based method for loop folding

We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported. >

[1]  Phn Peter Motion-adaptive intraframe transform coding of video signals , 1989 .

[2]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Alexandru Nicolau,et al.  Percolation based synthesis , 1991, DAC '90.

[4]  Edward S. Davidson,et al.  A multiminiprocessor system implemented through pipelining , 1974, Computer.

[5]  Mohamed I. Elmasry,et al.  Architectural synthesis for DSP silicon compilers , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[7]  Daniel Gajski,et al.  An effective methodology for functional pipelining , 1992, ICCAD.

[8]  Bruce D. Shriver,et al.  Some Experiments in Local Microcode Compaction for Horizontal Machines , 1981, IEEE Transactions on Computers.

[9]  Youn-Long Lin,et al.  A new integer linear programming formulation for the scheduling problem in data path synthesis , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Yu-Chin Hsu,et al.  Scheduling for functional pipelining and loop winding , 1991, 28th ACM/IEEE Design Automation Conference.

[11]  Edwin Hsing-Mean Sha,et al.  Rotation Scheduling: A Loop Pipelining Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[12]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[13]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Markku Renfors,et al.  The maximum sampling rate of digital filters under hardware speed constraints , 1981 .

[15]  Alice C. Parker,et al.  Tutorial on high-level synthesis , 1988, DAC '88.

[16]  Peter M. Kogge,et al.  The Architecture of Pipelined Computers , 1981 .

[17]  Mohamed I. Elmasry,et al.  SPAID: an architectural synthesis tool for DSP custom applications , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[18]  Keshab K. Parhi,et al.  Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding , 1991, IEEE Trans. Computers.

[19]  Peter B. Denyer,et al.  A new approach to pipeline optimisation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[20]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Emile H. L. Aarts,et al.  Efficiency improvements for force-directed scheduling , 1992, ICCAD.

[22]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[23]  T. Kailath,et al.  VLSI and Modern Signal Processing , 1984 .

[24]  Joos Vandewalle,et al.  An efficient microcode compiler for application specific DSP processors , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Daniel W. Dobberpuhl,et al.  The design and analysis of VLSI circuits , 1985 .

[26]  Shimon Even,et al.  Graph Algorithms , 1979 .

[27]  Sabih H. Gerez,et al.  Range-chart-guided iterative data-flow graph scheduling , 1992 .

[28]  Giovanni De Micheli,et al.  Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .