Damageless FeRAM integration process : Special issue on ferroelectric memory technology

A damageless FeRAM integration process has been developed for FeRAM embedded CMOS logic. Without changing logic device parameters, the effect of backend processes on a ferroelectric capacitor such as hydrogen attack and stress is eliminated by using hydrogen-free O 3 -TEOS SiO 2 and low thermal-expansion-coefficient interconnect. Good electrical properties are obtained for a 3×3μm PZT capacitor after integration processes including multi-layer metallization, passivation and packaging: 2Pr of more than 30μC/cm 2 and no fatigue during 10 9 switching cycles.