A survey of hardware signature implementations in multi-core systems
暂无分享,去创建一个
[1] Emilio L. Zapata,et al. Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets , 2013, IEEE Transactions on Parallel and Distributed Systems.
[2] Javier D. Bruguera,et al. FlexSig: Implementing flexible hardware signatures , 2012, TACO.
[3] Norman P. Jouppi,et al. Multi-Core Cache Hierarchies , 2011, Multi-Core Cache Hierarchies.
[4] Jeffrey T. Draper,et al. Improving Utilization of Hardware Signatures in Transactional Memory , 2013, IEEE Transactions on Parallel and Distributed Systems.
[5] David R. Cheriton,et al. SI-TM: reducing transactional memory abort rates through snapshot isolation , 2014, ASPLOS.
[6] Emilio L. Zapata,et al. Improving Signature Behavior by Irrevocability in Transactional Memory Systems , 2014, 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing.
[7] Qi Li,et al. SeTM: Efficient Execution of Speculative Threads with Hardware Transactional Memory , 2012, 2012 IEEE 18th International Conference on Parallel and Distributed Systems.
[8] Jae-il Jung,et al. Reducing false conflicts in signature-based eager hardware transactional memory , 2014 .
[9] Josep Torrellas,et al. Bulk Disambiguation of Speculative Threads in Multiprocessors , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[10] Oscar Plata,et al. LS-Sig: Locality-Sensitive Signatures for Transactional Memory , 2013, IEEE Transactions on Computers.