Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays

Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays Jason Luu Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 2014 As technology scaling, human creativity, and other factors open new markets for FPGAs, the architectures of such chips must continue to evolve to meet changing demands. However, public domain software tools available to explore future FPGA architectures have not kept pace with advances in the field. Furthermore, these tools often have strong architectural assumptions embedded within the source code itself. Thus, short of major software rewriting, this limits the use of these tools to simple variations of particular architectures. In this thesis, we describe contributions to a large open-source collaborative project, called Verilog-to-Routing (VTR), that relaxes such limitations by providing an extensive software infrastructure for FPGA architecture exploration and CAD research. This infrastructure includes modern benchmarks, sample architecture description files, and a CAD flow that can target a broad space of architectures. We then describe new techniques in the packing stage of the CAD flow, which allow the packer to both target FPGAs with modern architectural features, as well as adjust computational effort based on architectural complexity. Finally, we conduct an architecture experiment on hard adders and carry chains to show the new capabilities of the software infrastructure and to quantitatively answer questions about the actual effectiveness of these classical architectural features.

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