A multi-band fully differential fractional-N PLL for wideband reconfigurable wireless communication

A fractional-N PLL for multi-standard transceiver is presented. The tuning range covers dual bands of 0.38~6 GHz and 9~12 GHz. A high-speed ultra-band divide-by-2 circuit is designed to accomplish the frequency band of 0.3 to 13.7 GHz. A novel high isolation multiplexer is presented to achieve the frequency band selection in LO paths. This chip was implemented with 65 nm CMOS technology and the maximum current consumption is 20.05 mA at 1.2 V power supply. The measured typical phase noise of the PLL is -114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output and the reference spur and fractional spur are less than -48 dBc and -62.99 dBc respectively.