Power property analysis for CMOS integrated circuits

Power consumption has become one of the primary constraints of integrated circuit designs, especially for wireless communication environments and battery-operated applications. Some important power information is very needed to be known in design phases. In this paper, two parameters of variation and expectation rate (VER) and maximum-skew ratio (MSR) are defined along with expectation and variation to describe the complicated total power behavioral. To achieve accurate analysis of all these power properties, a quantified experimental method is proposed based on the existing dynamic and leakage power models and the results show the analysis environment and the parameters are very useful for low power and high performance circuit system designs

[1]  Kaushik Roy,et al.  Maximum power estimation for CMOS circuits using deterministic and statistic approaches , 1996, Proceedings of 9th International Conference on VLSI Design.

[2]  Ping Yang,et al.  A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Kaushik Roy,et al.  Maximum power estimation for CMOS circuits using deterministic and statistical approaches , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Wen-Tsong Shiue Leakage power estimation and minimization in VLSI circuits , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[5]  David Blaauw,et al.  Analysis and minimization techniques for total leakage considering gate oxide leakage , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  Kaushik Roy,et al.  COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits , 1997, ICCAD 1997.

[7]  Zuying Luo,et al.  Vector extraction for average total power estimation , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[8]  Kaushik Roy,et al.  Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  John N. Avaritsiotis,et al.  A Monte Carlo approach for maximum power estimation based onextreme value theory , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..