Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing

Memristive technology is still not mature enough for the very large-scale integration necessary to obtain practical value from neuromorphic computing. While nonvolatile floating-gate "synapse transistors" have been implemented in very large-scale integrated neuromorphic systems, their large footprint still constrains an upper bound on the overall performance. A two-terminal floating-gate memristive device can combine the technological maturity of the floating-gate transistor and the conceptual novelty of the memristor using a standard CMOS process. In this paper, we present a top-down computer aided design framework of the floating-gate memristive device and show its potential in neuromorphic computing. Our framework includes a Verilog-A model, small-signal schematics, a stochastic model, Monte-Carlo simulations, layout, DRC, LVS, and RC extraction.

[1]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[2]  Gert Cauwenberghs,et al.  Memristors Empower Spiking Neurons With Stochasticity , 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[3]  Farnood Merrikh-Bayat,et al.  Training and operation of an integrated neuromorphic network based on metal-oxide memristors , 2014, Nature.

[4]  L. Chua.  Memristor-The missing circuit element , 1971 .

[5]  Khaled N. Salama,et al.  Memristor-based memory: The sneak paths problem and solutions , 2013, Microelectron. J..

[6]  Eby G. Friedman,et al.  VTEAM – A General Model for Voltage Controlled Memristors , 2014 .

[7]  C.M. Compagnoni,et al.  Analytical Model for the Electron-Injection Statistics During Programming of Nanoscale nand Flash Memories , 2008, IEEE Transactions on Electron Devices.

[8]  Farnood Merrikh-Bayat,et al.  High-Performance Mixed-Signal Neurocomputing With Nanoscale Floating-Gate Memory Cell Arrays , 2018, IEEE Transactions on Neural Networks and Learning Systems.

[9]  C. Hu,et al.  Lucky-electron model of channel hot-electron injection in MOSFET'S , 1984 .

[10]  Yakov Roizin,et al.  Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing , 2019, Nature Electronics.

[11]  T.Y. Chan,et al.  The impact of gate-induced drain leakage current on MOSFET scaling , 1987, 1987 International Electron Devices Meeting.

[12]  C. Lee Giles,et al.  An analysis of noise in recurrent neural networks: convergence and generalization , 1996, IEEE Trans. Neural Networks.

[13]  G. W. Burr,et al.  Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element , 2015, 2014 IEEE International Electron Devices Meeting.

[14]  Carver A. Mead,et al.  Neuromorphic electronic systems , 1990, Proc. IEEE.

[15]  H-S Philip Wong,et al.  Memory leads the way to better computing. , 2015, Nature nanotechnology.

[16]  Chenming Hu,et al.  Lucky-electron model of channel hot-electron injection in MOSFET'S , 1984, IEEE Transactions on Electron Devices.

[17]  Paul E. Hasler,et al.  Single Transistor Learning Synapses , 1994, NIPS.

[18]  Sherif M. Sharroush,et al.  Subthreshold MOSFET transistor amplifier operation , 2009, 2009 4th International Design and Test Workshop (IDT).