Enabling design and simulation of massive parallel nanoarchitectures

Abstract A common element in emerging nanotechnologies is the increasing complexity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evaluated simultaneously. In several cases faced problems are known, but require a fresh re-think on the basis of different constraints not enforced by standard design tools. Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architectures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures. The tool we present is of aid in the design of circuits based on nanotechnologies, here discussed in the specific case of nanowire arrays, as best candidate for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDLs), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simulation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Results about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented.

[1]  Loïc Lagadec,et al.  Towards a framework for designing applications onto hybrid nano/CMOS fabrics , 2009, Microelectron. J..

[2]  P. Narayanan,et al.  FastTrack: Toward Nanoscale Fault Masking With High Performance , 2012, IEEE Transactions on Nanotechnology.

[3]  Guido Masera,et al.  Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Gianluca Piccinini,et al.  UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2 , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Charles M. Lieber,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001, Science.

[6]  Pritish Narayanan,et al.  Manufacturing pathway and associated challenges for nanoscale computational systems , 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

[7]  Mariagrazia Graziano,et al.  A flexible simulation methodology and tool for nanoarray-based architectures , 2010, 2010 IEEE International Conference on Computer Design.

[8]  K.L. Wang,et al.  More Than Moore's Law: Nanofabrics and Architectures , 2007, 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[9]  M. Zamboni,et al.  An NCL-HDL Snake-Clock-Based Magnetic QCA Architecture , 2011, IEEE Transactions on Nanotechnology.

[10]  Teng Wang,et al.  Latching on the wire and pipelining in nanoscale designs , 2004 .

[11]  Csaba Andras Moritz,et al.  Validating cascading of crossbar circuits with an integrated device-circuit exploration , 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

[12]  Csaba Andras Moritz,et al.  Integrated nanosystems with junctionless crossed nanowire transistors , 2011, 2011 11th IEEE International Conference on Nanotechnology.

[13]  Mark Mohammad Tehranipoor.  Defect tolerance for molecular electronics-based nanofabrics using built-in self-test procedure , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[14]  Massimo Ruo Roch,et al.  Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders , 2013, IEEE Transactions on Nanotechnology.

[15]  P. Lugli,et al.  Electronic transport modeling with HSPICE in random CNT networks , 2012, 2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO).

[16]  Teng Wang,et al.  Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Neal G. Anderson,et al.  Tight-binding implementation of the microcanonical approach to transport in nanoscale conductors: Generalization and analysis , 2010 .

[18]  Gianluca Piccinini,et al.  Bis-Ferrocene Molecular QCA Wire: Ab Initio Simulations of Fabrication Driven Fault Tolerance , 2013, IEEE Transactions on Nanotechnology.

[19]  Wei Lu,et al.  TOPICAL REVIEW: Semiconductor nanowires , 2006 .

[20]  Mariagrazia Graziano,et al.  Nanofabric power analysis: Biosequence alignment case study , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[21]  T. Cao,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001 .

[22]  P. Narayanan,et al.  Comparison of analog and digital nanosystems: Issues for the nano-architect , 2008, 2008 2nd IEEE International Nanoelectronics Conference.

[23]  André DeHon,et al.  Nanowire-based programmable architectures , 2005, JETC.

[24]  P. Narayanan,et al.  Image Processing Architecture for Semiconductor Nanowire Based Fabrics , 2008, 2008 8th IEEE Conference on Nanotechnology.

[25]  Andreas Mayr,et al.  CrossNets: High‐Performance Neuromorphic Architectures for CMOL Circuits , 2003, Annals of the New York Academy of Sciences.

[26]  Teng Wang,et al.  CMOS Control Enabled Single-Type FET NASIC , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[27]  Christina De Meyer.  Activities of the Emerging Research Devices (ERD) chapter of the International Technology Roadmap for Semiconductors , 2004 .

[28]  Csaba Andras Moritz,et al.  Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation , 2013, JETC.

[29]  P. Narayanan,et al.  Integrated Device–Fabric Explorations and Noise Mitigation in Nanoscale Fabrics , 2012, IEEE Transactions on Nanotechnology.

[30]  Mariagrazia Graziano,et al.  Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison? , 2011, IEEE Design & Test of Computers.

[31]  P. Narayanan,et al.  Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics , 2009, IEEE Transactions on Nanotechnology.

[32]  Mariagrazia Graziano,et al.  A technology aware magnetic QCA NCL-HDL architecture , 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

[33]  George Bourianoff,et al.  Emerging Nanoscale Memory and Logic Devices: A Critical Assessment , 2008, Computer.

[34]  Loïc Lagadec,et al.  Regular 2D NASIC-based architecture and design space exploration , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[35]  Israel Koren,et al.  Nanoscale Application Specific Integrated Circuits , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[36]  Z. Patitz,et al.  A Floorprint-based Defect Tolerance for Nano-scale Application-Specific IC , 2008, 2008 IEEE Instrumentation and Measurement Technology Conference.

[37]  Tohru Yamamoto,et al.  Two-dimensional molecular electronics circuits. , 2002, Chemphyschem : a European journal of chemical physics and physical chemistry.