Cell-to-array thermal-aware analysis of stacked RRAM

The crossbar resistive random access memory (RRAM) has been studied extensively due to its low-power, low-cost, high density and nonvolatile characteristics. However, the dependence of RRAM performance parameters on temperature, from cell to array level, is less explored. Particularly, thin-film based RRAM that is integrated into 3D ICs is subject to severe thermal conditions. Hence, temperature dependence of RRAM behavior needs to be well understood in order to construct the most effective thermal management strategy for these systems. In this paper, a detailed RRAM device thermal model is proposed. Our experiments show that the temperature of the surrounding environment critically impacts the RRAM readout margin, which in turn, jeopardizes its promised advantages for high-density stacked integration. Our thermal model can be utilized at the architectural level to predict the latency variation in the RRAM memory as a function of the thermal environment and drive thermal management policies for the 3D IC.