Frontiers of timing

The Integrated Circuit (IC) industry is approaching an important transition. For decades, the persistent downscaling of feature sizes has enabled a rapidly growing integration and exponentially increasing circuit performance. But process variations and device aging are posing increasingly serious challenges to the sustainability of the current development model of integrated circuits. Accordingly, timing, as one of the core performance metrics, needs to evolve with these new challenges. New timing paradigms are already appearing on the horizon. In this extended abstract, timing challenges resulting from process variations and aging will be reviewed. Techniques to take these effects into account will be discussed, such as efficient aging aware transistor/gate modeling. Post-silicon tuning is covered as a promising technique to react to these timing challenges. Furthermore, techniques to push timing beyond its traditional limit, such as modeling the interdependence of setup time and hold time, will be reviewed. Together, these techniques represent a potential future framework for timing in the nanometer era.