A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion

Time-to-digital converters (TDCs) are promising building blocks for the digitalization of mixed-signal functionality in ultra-deep-submicron CMOS technologies. A short survey on state-of-the-art TDCs is given. A high-resolution TDC with low latency and low dead-time is proposed, where a coarse time quantization derived from a differential inverter delay-line is locally interpolated with passive voltage dividers. This high-resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated by a 90 nm demonstrator which uses a 4x interpolation and provides a time domain resolution of 4.7 ps. An integral nonlinearity of 1.2 LSB and a differential nonlinearity of 0.6 LSB are achieved. The resolution restrictions imposed by an uncertainty of the stop signal and local variations are derived theoretically.

[1]  B.M. Helal,et al.  A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation , 2007, 2007 IEEE Symposium on VLSI Circuits.

[2]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[3]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines for the digitization of short time intervals , 1993 .

[4]  Poras T. Balsara,et al.  A wide-range, high-resolution, compact, CMOS time to digital converter , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[5]  Poki Chen,et al.  A CMOS pulse-shrinking delay element for time interval measurement , 2000 .

[6]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[7]  J. Kostamovaara,et al.  A CMOS time-to-digital converter with better than 10 ps single-shot precision , 2006, IEEE Journal of Solid-State Circuits.

[8]  A. Abidi,et al.  A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue , 2007, 2007 IEEE Symposium on VLSI Circuits.

[9]  R. J. van de Plassche,et al.  An 8-b 650-MHz folding ADC , 1992 .

[10]  D. Schmitt-Landsiedel,et al.  Variation tolerant high resolution and low latency time-to-digital converter , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[11]  T. Rahkonen,et al.  A high resolution time-to-digital converter based on time-to-voltage interpolation , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[12]  R. Nutt.  Digital Time Intervalometer , 1968 .

[13]  Poras T. Balsara,et al.  1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Stephan Henzler,et al.  90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[15]  O. Moreira-Tamayo,et al.  All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.