Architecture implementation using the machine description language LISA

The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design implementation. The LISA processor design platform (LPDP) based on machine descriptions in the LISA language provides one common environment for these design phases. Required software tools for architecture exploration and application development can be generated from one sole specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The derivation of the architectural structure, decoder and even approaches for the implementation of the data path are presented. Moreover the synthesis results of a generated and a handwritten implementation of a low-power DVB-T post processing unit are compared.

[1]  Wolfgang Rosenstiel,et al.  System Level Design Using the SystemC Modeling Platform , 2001 .

[2]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[3]  Heinrich Meyr,et al.  LISA—machine description language for cycle-accurate models of programmable DSP architectures , 1999, DAC '99.

[4]  Heinrich Meyr,et al.  Generating production quality software development tools using a machine description language , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  Edwin A. Harcourt,et al.  Generation of software tools from processor descriptions for hardware/software codesign , 1997, DAC.

[6]  H. Meyr,et al.  ICORE: a low-power application specific instruction set processor for DVB-T acquisition and tracking , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

[7]  Alois Knoll,et al.  Generation of hardware machine models from instruction set descriptions , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[8]  Srinivas Devadas,et al.  A methodology for accurate performance evaluation in architecture exploration , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[9]  Heinrich Meyr,et al.  A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..