Critical issues in overlay metrology

In this paper, following an overview of overlay metrology, the difficult relationship of overlay with device performance and yield is discussed and supported with several examples. This is followed by a discussion of the impending collision of metrology equipment performance and “real” process tolerances for sub 0.18 um technologies. This convergence of tolerance and performance is demonstrated to lead to the current emergence of real-time overlay modeling in a feed-forward/feedback process environment and the associated metrology/sampling implications. This modeling takes advantage of the wealth of understanding concerning the systematic behavior of overlay registration errors. Finally, the impact of new process technologies (RET, OAI, CPSM, CMP, & etc.) on the measurement target is discussed and shown to de-stabilize overlay performance on standard overlay measurement target designs.

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