Using the BACH trace collection mechanism to characterize the SPEC 2000 integer benchmarks

Computer systems are modeled before construction to minimize errors and performance bottlenecks. A common modeling approach is to build software models of computer system components, and use realistic trace data as input. This methodology is commonly referred to as trace-driven simulation. Trace-driven simulation can be very accurate if both the system model and input trace data represent the systems under test. The accuracy of the model is typically under the control of the research, but little or no trace data is available that accurately represents current of future workloads. The objective of this work is to describe the Brigham Young University Address Collection Hardware (BACH) and illustrate the types of traces that we can collect. These traces will be made available to others in a national trace repository(http://traces.byu.edu). We also provide some cache performance statistics for the SPEC 2000 integer benchmarks.

[1]  James K. Archibald,et al.  BACH: a hardware monitor for tracing microprocessor-based systems , 1993, Microprocessors and microsystems.

[2]  Brian N. Bershad,et al.  The impact of operating system structure on memory system performance , 1994, SOSP '93.

[3]  Peter A. Sandon,et al.  NStrace: A bus-driven instruction trace tool for PowerPC microprocessors , 1997, IBM J. Res. Dev..

[4]  Trevor Mudge,et al.  Monster : a tool for analyzing the interaction between operating systems and computer architectures , 1992 .

[5]  Anoop Gupta,et al.  Complete computer system simulation: the SimOS approach , 1995, IEEE Parallel Distributed Technol. Syst. Appl..

[6]  B. Gopinath,et al.  Compression-Based Program Characterization for Improving Cache Memory Performance , 1997, IEEE Trans. Computers.

[7]  Mark Horowitz,et al.  ATUM: a new technique for capturing address traces using microcode , 1986, ISCA '86.

[8]  James K. Archibald,et al.  Incomplete Trace Data and Trace Driven Simulation , 1993, MASCOTS.

[9]  James K. Archibald,et al.  The inaccuracy of trace-driven simulation using incomplete multiprogramming trace data , 1996, Proceedings of MASCOTS '96 - 4th International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

[10]  Douglas W. Clark,et al.  Cache Performance in the VAX-11/780 , 1983, TOCS.

[11]  James K. Archibald,et al.  Low-power memory hierarchies: an argument for second-level caches , 1998, Microprocess. Microsystems.

[12]  David W. Wall,et al.  Generation and analysis of very long address traces , 1990, ISCA '90.

[13]  J. Kelly Flanagan,et al.  Constructing instruction traces from cache-filtered address traces (CITCAT) , 1996, CARN.

[14]  Brent E. Nelson,et al.  Transaction processing workloads-a comparison to the SPEC benchmarks using memory hierarchy performance studies , 1996, Proceedings of MASCOTS '96 - 4th International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

[15]  Doug Burger,et al.  Evaluating Future Microprocessors: the SimpleScalar Tool Set , 1996 .

[16]  J. Kelly Flanagan.  A new methodology for accurate trace collection and its application to memory hierarchy performance modeling , 1993 .

[17]  Alan Eustace,et al.  ATOM - A System for Building Customized Program Analysis Tools , 1994, PLDI.