AN AMBA-COMPLIANT MOTION ESTIMATOR FOR H.264 ADVANCED VIDEO CODING

1 Supported in part by the National Science Council, R.O.C., under Grants No. NSC 92-2218-E-007-023, NSC 92-2220-E007-009, and NSC 92-2220-E-007-017, by the Ministry of Economics Affairs, R.O.C., under Grant No. 92-EC-17-A-03S1-0002, and by Taiwan Semiconductor Manufacturing Corp. (TSMC) under Grant No. 93A0002EA. Abstract –We propose a 2D VLSI architecture with 256 processing elements and a computation result reuse methodology for full search variable block size motion estimation (FSVBSME) in the next generation video coding standard H.264/AVC. Our pipelined engine can complete matching a candidate macroblock in every clock cycle. We implement a prototype on an SOC platform with a 32-bit RISC CPU core and field programmable gate array (FPGA) module. We equip the hardware accelerator with an AMBA-AHB on-chip-bus interface. Experimental results show that our proposed hardware accelerator delivers 480X speed-up when compared with software running at the same clock rate.

[1]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[2]  Jimin Cheon,et al.  Analysis of the Ramp Signal Noise Source in the CIS with the Column-wise ADC , 2004 .

[3]  Liang-Gee Chen,et al.  Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264 , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[4]  Youngcheol Chae,et al.  Effect of Ramp Signal Noise on CMOS Image Sensor with Column-wise CDS/ADC , 2004 .

[5]  Jean Luc Philippe,et al.  A formal technique for hardware interface design , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[6]  John V. McCanny,et al.  A VLSI architecture for advanced video coding motion estimation , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[7]  Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003 , 2003 .

[8]  Chein-Wei Jen,et al.  On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture , 2002, IEEE Trans. Circuits Syst. Video Technol..