High frame rate VGA CMOS image sensor using two-step single slope ADCs

A column-parallel two step Single Slope Analog-to-Digital Converter (SS ADC) for high frame rate VGA CMOS Image Sensor. The proposed circuit improves the sampling rate while maintaining the architecture of the conventional SS ADC for high frame rate CIS. The proposed structure does not have analog memory capacitor for storing the value of the first ramp step. The proposed two-step SS ADC has a 12bit resolution and conversion time of 6.3μs at 62.5MHz clock frequency. The VGA CIS using two step SS ADC has the maximum frame rate of upto 320 frames/s.

[1]  Bedabrata Pain,et al.  CMOS active pixel sensor with on-chip successive approximation analog-to-digital converter , 1997 .

[2]  Gunhee Han,et al.  A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs , 2009 .

[3]  A. El Gamal,et al.  CMOS image sensors , 2005, IEEE Circuits and Devices Magazine.

[4]  S. Decker,et al.  A 256/spl times/256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[5]  Woodward Yang,et al.  An integrated 800/spl times/600 CMOS imaging system , 1999 .

[6]  M.F. Snoeij,et al.  Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors , 2007, IEEE Journal of Solid-State Circuits.

[7]  K. Findlater,et al.  SXGA pinned photodiode CMOS image sensor in 0.35 /spl mu/m technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[8]  A. Suzuki,et al.  High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.