Fabrication and Characterization of Annular Copper Through-Silicon via for Passive Interposer Applications

This paper develops an annular copper through silicon via (TSV) integration process. Additives, including accelerator, suppressor, and leveler, with different concentrations are employed in the methanesulfonic-based electrolyte. Besides, other influence factors, including current density, forced convection, and environment temperature, are also taken into consideration for the sake of annular TSV filling. A same number of samples with annular and fully filled copper TSV, in the same structure parameters and technological conditions, are fabricated, respectively. Electroplating experiment, X-ray inspection, electrical testing as well as reliability testing are performed in order to compare the characterization of the two integration processes. All test results support this proposed annular TSV integration approach has great application prospect for passive interposer applications.

[1]  Katsuyuki Sakuma,et al.  3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections , 2008, IBM J. Res. Dev..

[2]  Fengjuan Wang,et al.  Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV) , 2013, IEICE Electron. Express.

[3]  F. Su,et al.  Mechanical and electrical reliability assessment of bump-less wafer-on-wafer integration with one-time bottom-up TSV filling , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[4]  V. Lee,et al.  Development of 3D silicon module with TSV for system in packaging , 2008, 2008 58th Electronic Components and Technology Conference.

[5]  M. Kunz,et al.  Microstructure Evolution and Defect Formation in Cu Through-Silicon Vias (TSVs) During Thermal Annealing , 2012, Journal of Electronic Materials.

[6]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[7]  Wen-Yan Yin,et al.  Modeling of a pair of annular through silicon vias (TSV) , 2011, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

[8]  K. Vaidyanathan,et al.  Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps , 2008, 2008 58th Electronic Components and Technology Conference.

[9]  Y. Lamy,et al.  mmW characterization of wafer level passivation for 3D silicon interposer , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[11]  Jong-In Ryu,et al.  High density and low-cost silicon interposer using thin-film and organic lamination processes , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[12]  J. Chen,et al.  Numerical modeling and experimental verification of through silicon via (TSV) filling in presence of additives , 2014 .

[13]  Yasumitsu Orii,et al.  Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package , 2012 .

[14]  B. Xie,et al.  Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[15]  F. Che,et al.  Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication , 2012, Journal of Electronic Materials.

[16]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[17]  J. Lau.  Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration , 2011, 2011 International Symposium on Advanced Packaging Materials (APM).

[18]  B. Verlinden,et al.  Influence of annealing conditions on the mechanical and microstructural behavior of electroplated Cu-TSV , 2010 .

[19]  H. Miura,et al.  Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps , 2012 .

[20]  Tai Chong Chai,et al.  Development of Large Die Fine-Pitch Cu/Low- $k$ FCBGA Package With Through Silicon via (TSV) Interposer , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[21]  Xiaowu Zhang,et al.  Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.

[22]  Hong Wang,et al.  Effect of External Factors on Copper Filling in 3D Integrated Through-Silicon-Vias (TSVs) , 2015 .

[23]  John H. Lau,et al.  3D IC Integration with TSV Interposers for High Performance Applications , 2010 .

[24]  Yufeng Jin,et al.  Electrical characterization of cylindrical and annular TSV for combined application thereof , 2011, 2011 12th International Conference on Electronic Packaging Technology and High Density Packaging.