Hardware Implementation of High Throughput RC4 algorithm

In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment of system throughput and three times reduction of RAM resource compared to the recent architectures. The proposed implementation supports variable key length from 8 to 128 bits and achieves 80 MB/s throughput at 160 MHz operating frequency. It aims to support the WEP security in the MAC layer of 600 Mbps 4×4 MIMO wireless LAN system based on IEEE 802.11n standard.

[1]  Bernard P. Zajac.  Applied cryptography: Protocols, algorithms, and source code in C , 1994 .

[2]  O. Koufopavlou,et al.  Hardware implementation of the RC4 stream cipher , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[3]  S.J.E. Wilton,et al.  A CPLD-based RC4 cracking system , 1999, Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411).

[4]  Subhamoy Maitra,et al.  One Byte per Clock: A Novel RC4 Hardware , 2010, INDOCRYPT.

[5]  Wang Zuo,et al.  An Intelligent Multi-Port Memory , 2008, IITA 2008.

[6]  Bruce Schneier,et al.  Fast Software Encryption: Designing Encryption Algorithms for Optimal Software Speed on the Intel Pentium Processor , 1997, FSE.

[7]  Panu Hämäläinen,et al.  Hardware implementation of the improved WEP and RC4 encryption algorithms for wireless terminals , 2000, 2000 10th European Signal Processing Conference.

[8]  Wang Zuo.  An Intelligent Multi-Port Memory , 2008, 2008 International Symposium on Intelligent Information Technology Application Workshops.

[9]  Philip Heng Wai Leong,et al.  A massively parallel RC4 key search engine , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.