The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.175 /spl mu/m cell array for the first time. The FBC is a one-transistor gain cell, which is a suitable structure for the future embedded DRAM on SOI wafer. The memory cell layout and the process integration have been designed from the viewpoint of the logic process compatibility without sacrificing the data retention characteristics. The salicide process with the poly-Si plug is implemented into the process integration. The most important device characteristics for realizing the FBC is the threshold voltage difference (/spl Delta/ Vth) of the cell transistor between "1" state and "0" state. The key device parameters in order to enlarge the /spl Delta/ Vth are experimentally clarified. A /spl Delta/ Vth of 0.4 V has been obtained, which leads to 99.77% function bit yield of 96 Kbit ADM (Array Diagnostic Monitor). The retention time of 5 sec has been realized at the room temperature.