A Mostly-Digital Variable-Rate Continuous-Time
暂无分享,去创建一个
[1] Gabor C. Temes,et al. Understanding Delta-Sigma Data Converters , 2004 .
[2] A. Sripad,et al. A necessary and sufficient condition for quantization errors to be uniform and white , 1977 .
[3] Bernhard E. Boser,et al. Simulating and testing oversampled analog-to-digital converters , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Michael H. Perrott,et al. A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, VLSIC 2008.
[5] Ian Galton. Granular quantization noise in a class of delta-sigma modulators , 1994, IEEE Trans. Inf. Theory.
[6] K. Nguyen,et al. A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[7] Min C. Park,et al. A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[8] Frank Opteynde. A maximally-digital radio receiver front-end , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[9] M. Høvin,et al. Delta-sigma modulators using frequency-modulated intermediate values , 1997, IEEE J. Solid State Circuits.
[10] Ian Galton,et al. A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.
[11] U. Wismar,et al. A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.
[12] Jaewook Kim,et al. A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[13] Haiming Tang,et al. Time-referenced single-path multi-bit /spl Delta//spl Sigma/ ADC using a VCO-based quantizer , 2000 .
[14] Ian Galton,et al. Digital Background Correction of Harmonic Distortion in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[15] Thomas Blon,et al. A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .
[16] Takashi Morie,et al. The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer , 1999 .