A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.

[1]  Erdal Oruklu,et al.  Fast memory addressing scheme for radix-4 FFT implementation , 2009, 2009 IEEE International Conference on Electro/Information Technology.

[2]  Pei-Yun Tsai,et al.  A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Dionysios I. Reisis,et al.  Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Chen-Yi Lee,et al.  A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Sau-Gee Chen,et al.  A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Feng Yu,et al.  A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Mario Garrido Gálvez.  Efficient hardware architectures for the computation of the FFT and other related signal processing algorithms in real time , 2009 .

[8]  Jesús Grajal,et al.  Optimum Circuits for Bit Reversal , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Jesús Grajal,et al.  Pipelined Radix-$2^{k}$ Feedforward FFT Architectures , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[11]  Lars Wanhammar,et al.  A hardware efficient control of memory addressing for high-performance FFT processors , 2000, IEEE Trans. Signal Process..

[12]  D. Cohen.  Simplified control of FFT hardware , 1976 .

[13]  Myung Hoon Sunwoo,et al.  New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Jesús Grajal,et al.  Efficient Memoryless Cordic for FFT Computation , 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.