Provably Correct High-level Timing Analysis Without Path Sensitization
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[1] Fadi J. Kurdahi,et al. Combined topological and functionality based delay estimation using a layout-driven approach for high level applications , 1994, EURO-DAC '92.
[2] Nikil D. Dutt,et al. Rapid estimation for parameterized components in high-level synthesis , 1993, IEEE Trans. Very Large Scale Integr. Syst..
[3] Régis Leveugle,et al. Taking advantage of high level functional information to refine timing analysis and timing information , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[4] Sharad Malik,et al. Delay computation in combinational logic circuits: theory and algorithms , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[5] Reinaldo A. Bergamaschi,et al. The effects of false paths in high-level synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[6] Daniel Tabak,et al. Microcontrollers: architecture, implementation, and programming , 1992 .
[7] Sujit Dey,et al. Clock Period Optimization During Resource Sharing and Assignment , 1994, 31st Design Automation Conference.
[8] Robert K. Brayton,et al. Timing analysis and delay-fault test generation using path-recursive functions , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[9] Sharad Malik,et al. Functional timing analysis using ATPG , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[10] F.J. Kurdahi,et al. Combined topological and functionality based delay estimation using at layout-driven approach for high level applications , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[11] Don MacMillen,et al. ISIS: a system for performance driven resource sharing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[12] Viraphol Chaiyakul,et al. Accurate layout area and delay modeling for system level design , 1992, ICCAD.
[13] Hugo De Man,et al. Static Timing Analysis of Dynamically Sensitizable Paths , 1989, 26th ACM/IEEE Design Automation Conference.
[14] Andreas Kuehlmann,et al. Timing analysis in high-level synthesis , 1992, ICCAD.
[15] Robert K. Brayton,et al. Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[16] David Hung-Chang Du,et al. Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.