α-coral: a multigrain, multithreaded processor architecture

Recently popularized hardware multithreading (HMT) architectures, such as SMT, Multiscalar and Terra do not provide flexible and efficient methods of thread management and synchronization in hardware. The α-Coral architecture is a tool for investigation of a more dynamic approach to thread management. Unlike other architectures, there are no strict requirements on timing and size of threads, and no static partitioning of resources. α-Coral provides for simultaneous multiprogramming and multithreading environment, which is mostly managed in hardware. To other architectures, α-Coral adds on demand register allocation, fast variable size thread creation and destruction, as well as quick synchronization through a shared register file. While other architectures attempt to port existing compilers, the α-Coral architecture is supported by a custom compiler system. This system provides for a simple method of mapping hierarchical internal representation of the program to variable size threads. This paper examines a new approach to hardware multithreading, involving minimal extensions to the instruction set of conventional RISC superscalar architectures. The α-Coral architecture and compiling support introduce a multi-grain multithreaded architecture which extends wide-superscalar processor cores to support hierarchical multithreading. A simulator was developed and results are presented to demonstrate the feasibility of our design approach.