Verification Methodology for Self-Repairable Memory Systems

With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors

[1]  Magdy S. Abadir,et al.  PowerPC/sup (TM)/ array verification methodology using formal techniques , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[2]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Reinaldo A. Bergamaschi,et al.  Designing systems-on-chip using cores , 2000, DAC.

[4]  Dilip K. Bhavsar An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264 , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Randal E. Bryant,et al.  Formal verification of memory circuits by switch-level simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[7]  Randal E. Bryant,et al.  Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Alberto L. Sangiovanni-Vincentelli,et al.  Interface-based design , 1997, DAC.

[9]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[10]  Jin-Fu Li,et al.  An Infrastructure IP for Repairing Multiple RAMs in SOCs , 2006, 2006 International Symposium on VLSI Design, Automation and Test.

[11]  Keiichi Higeta,et al.  Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[12]  Steffen Paul,et al.  Memory built-in self-repair using redundant words , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[13]  Magdy S. Abadir,et al.  Experience in Validation of PowerPCTM Microprocessor Embedded Arrays , 1999, J. Electron. Test..

[14]  Jin-Fu Li,et al.  A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs , 2006, 2006 IEEE International Test Conference.

[15]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  Jin-Fu Li Efficient block-level connectivity verification algorithms for embedded memories , 2004 .

[17]  Jin-Fu Li,et al.  A built-in self-repair scheme for semiconductor memories with 2-d redundancy , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[18]  Kwang-Ting Cheng,et al.  Combining ATPG and symbolic simulation for efficient validation of embedded array systems , 2002, Proceedings. International Test Conference.

[19]  K. Antreich,et al.  Handling special constructs in symbolic simulation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[20]  K. Ishibashi,et al.  A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[21]  Joseph Rayhawk,et al.  At-speed built-in self-repair analyzer for embedded word-oriented memories , 2004, 17th International Conference on VLSI Design. Proceedings..

[22]  Jing-Yang Jou,et al.  On automatic-verification pattern generation for SoC withport-order fault model , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Kazumasa Yanagisawa,et al.  A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit , 2002 .