Scaling studies of CMOS SRAM soft-error tolerances—From 16K to 256K

The processing and design geometric scaling effects on the soft-error tolerance levels of the 16K 2-µm technology and the 256K 1-µm technology CMOS SRAMs are separated by fabricating the 16K 2-µm design with the 1-µm process. Although the 1-µm twin-tub process is inherently more tolerant than the p-well process to soft errors, the densely packed 1-µm memory cells become very soft because of the dominant effect of the channel width reduction. An advanced device-plus-circuit simulator was used to calculate the differential contribution from each of the vertical and lateral dimensional changes involved in the technology transition. Good agreement between the simulations and the experimental data is reached by properly correcting the 2D model to account for the phenomenal saturation effect involving very heavy ions.