Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs

Recent advances in three-dimensional integrated circuits (3D-ICs) offer a new dimension of design exploration at traditional physical architecture of datapath components. The emerging monolithic inter-tier vias (MIVs) provides more advantages over through-silicon vias (TSVs) in terms of higher integration density and lower design overhead. In this work, we develop a performance-driven framework which uses simulated annealing to produce gate-level 3D placement layout for rotation shifter and right arithmetic shifter design. Compared to the optimum 2D layout, the critical path of our solution is much shorter with limited overhead on total wirelength. Our work indicates that by gatelevel 3D-IC integration, the new physical dimension can be well leveraged with improvement on both performance and power of shifter design.

[1]  Giovanni De Micheli,et al.  CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[2]  Martin D. F. Wong,et al.  Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[3]  Mark A. Hillebrand,et al.  How to half wire lengths in the layout of cyclic shifters , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[4]  Sung Kyu Lim,et al.  Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[5]  Carl Sechen,et al.  Timing Driven Placement for Large Standard Cell Circuits , 1995, 32nd Design Automation Conference.

[6]  Jason Cong,et al.  A multilevel analytical placement for 3D ICs , 2009, 2009 Asia and South Pacific Design Automation Conference.

[7]  M.D. Ercegovac,et al.  Effect of wire delay on the design of prefix adders in deep-submicron technology , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[8]  Vaughn Betz,et al.  Timing-driven placement for FPGAs , 2000, FPGA '00.

[9]  Sorin Cotofana,et al.  3D stacked wide-operand adders: A case study , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

[10]  Sung Kyu Lim,et al.  High-density integration of functional modules using monolithic 3D-IC technology , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[11]  Yi Zhu,et al.  An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization , 2007, 2007 Asia and South Pacific Design Automation Conference.

[12]  Scott Hauck,et al.  Enhancing timing-driven FPGA placement for pipelined netlists , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[13]  Jason Cong,et al.  Thermal-driven multilevel routing for 3-D ICs , 2005, Asia and South Pacific Design Automation Conference.