On-Chip Communication Network: User Manual V1.0.1
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K. Varnali | Francesco Papariello | M. Coppola | Stephane Curaba | Giuseppe Maruccia | Miltos Grammatikakis
[1] Leslie Lamport,et al. Distributed snapshots: determining global states of distributed systems , 1985, TOCS.
[2] Alain Greiner,et al. A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.
[3] S. Wicker. Error Control Systems for Digital Communication and Storage , 1994 .
[4] Miltos D. Grammatikakis,et al. IPSIM: systemc 3.0 enhancements for communication refinement , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[5] Sujit Dey,et al. Evaluation of the traffic-performance characteristics of system-on-chip communication architectures , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[6] Srinivasan Parthasarathy,et al. An Efficient Algorithm for Concurrent Priority Queue Heaps , 1996, Inf. Process. Lett..
[7] Flaviu Cristian,et al. Probabilistic clock synchronization , 1989, Distributed Computing.
[8] Luca Benini,et al. Low power error resilient encoding for on-chip data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[9] LamportLeslie. Time, clocks, and the ordering of events in a distributed system , 1978 .
[10] Radu Marculescu,et al. Towards on-chip fault-tolerant communication , 2003, ASP-DAC '03.
[11] Martti Forsell,et al. A Scalable High-Performance Computing Solution for Networks on Chips , 2002, IEEE Micro.
[12] Richard B. Fair,et al. Integrated hierarchical design of microelectrofluidic systems using SystemC , 2002 .
[13] Mani B. Srivastava,et al. A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[14] Daniel D. Gajski,et al. SPECC: Specification Language and Methodology , 2000 .
[15] Alberto L. Sangiovanni-Vincentelli,et al. Coping with Latency in SOC Design , 2002, IEEE Micro.
[16] Israel Koren,et al. STATS: A framework for microprocessor and system-level design space exploration , 1999, J. Syst. Archit..
[17] Trung A. Diep,et al. VMW: A Visualization-Based Microarchitecture Workbench , 1995, Computer.
[18] Martin Peschke,et al. Design and Validation of Computer Protocols , 2003 .
[19] V.D. Zivkovic,et al. Design space exploration of streaming multiprocessor architectures , 2002, IEEE Workshop on Signal Processing Systems.
[20] Anant Agarwal,et al. Scalability of parallel machines , 1991, CACM.
[21] Bran Selic,et al. Real-time object-oriented modeling , 1994, Wiley professional computing.
[22] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[23] Theodore Johnson,et al. A Nonblocking Algorithm for Shared Queues Using Compare-and-Swap , 1994, IEEE Trans. Computers.
[24] Sujit Dey,et al. Design space exploration for optimizing on-chip communication architectures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[25] Bill Salefski,et al. System Level Design for SOC’s , 2001 .
[26] Leslie Lamport,et al. Time, clocks, and the ordering of events in a distributed system , 1978, CACM.
[27] F. Schirrmeister,et al. Methodology and technology for virtual component driven hardware/software co-design on the system-level , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[28] Miltos D. Grammatikakis,et al. Parallel System Interconnections and Communications , 2000 .
[29] Alberto L. Sangiovanni-Vincentelli,et al. Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[30] Alberto L. Sangiovanni-Vincentelli,et al. System design: traditional concepts and new paradigms , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).
[31] Maged M. Michael,et al. Simple, fast, and practical non-blocking and blocking concurrent queue algorithms , 1996, PODC '96.
[32] Pierre G. Paulin,et al. StepNP: A System-Level Exploration Platform for Network Processors , 2002, IEEE Des. Test Comput..
[33] Diederik Verkest,et al. System level design using C++ , 2000, DATE '00.
[34] Erwin A. de Kock,et al. COSY communication IP's , 2000, Proceedings 37th Design Automation Conference.
[35] Thomas A. Henzinger,et al. INTERFACE-BASED DESIGN , 2005 .
[36] Ali Poursepanj,et al. The PowerPC performance modeling methodology , 1994, CACM.
[37] Alberto L. Sangiovanni-Vincentelli,et al. Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[38] Dennis Shasha,et al. Locking without blocking: making lock based concurrent data structure algorithms nonblocking , 1992, PODS '92.
[39] A. Dewey,et al. Behavioral modeling of microelectromechanical systems (MEMS) with statistical performance-variability reduction and sensitivity analysis , 2000 .
[40] Naoaki Yamanaka,et al. Architectural choices in large scale ATM switches , 1998 .
[41] Colin J. Fidge,et al. Partial orders for parallel debugging , 1988, PADD '88.
[42] Claudio Turchetti,et al. Transaction-level models for AMBA bus architecture using SystemC 2.0 [SOC applications] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[43] Miltos D. Grammatikakis,et al. Software for Multiprocessor Networks on Chip , 2003, Networks on Chip.