Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

[1]  Chan-Hong Park,et al.  A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[2]  Behzad Razavi.  RF CMOS transceivers for cellular telephony , 2003, IEEE Commun. Mag..

[3]  Mustapha Slamani,et al.  A low-cost test solution for wireless phone RFICs , 2003, IEEE Commun. Mag..

[4]  Ali M. Niknejad,et al.  Design, Simulation and Applications of Inductors and Transformers for Si RF ICs , 2006 .

[5]  Martin Margala,et al.  A current sensor for on-chip, non-intrusive testing of RF systems , 2004, 17th International Conference on VLSI Design. Proceedings..

[6]  J.C. Leete,et al.  A 2.4 GHz CMOS transceiver for Bluetooth , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[7]  Michael S. Heutmaker,et al.  An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan , 1999, IEEE Commun. Mag..

[8]  M. Jarwala,et al.  End-to-end test strategy for wireless systems , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[9]  R. Gupta,et al.  Parasitic-aware design and optimization of CMOS RF integrated circuits , 1998, 1998 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.98CH36182).

[10]  Abhijit Chatterjee,et al.  Signature analysis for analog and mixed-signal circuit test response compaction , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..