SIRM: Shift Insensitive Racetrack Main Memory
暂无分享,去创建一个
Youyou Lu | Jiwu Shu | Hongbin Zhang | Bo Wei
[1] Kaushik Roy,et al. TapeCache: a high density, energy efficient cache based on domain wall memory , 2012, ISLPED '12.
[2] S. Parkin,et al. Magnetic Domain-Wall Racetrack Memory , 2008, Science.
[3] Hai Li,et al. Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power , 2015, The 20th Asia and South Pacific Design Automation Conference.
[4] Jiwu Shu,et al. Exploring main memory design based on racetrack memory technology , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).
[5] Jiwu Shu,et al. Exploring data placement in racetrack memory based scratchpad memory , 2015, 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA).
[6] Cong Xu,et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[8] Jiang Nan,et al. Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.
[9] Edwin Hsing-Mean Sha,et al. Optimizing data placement for reducing shift operations on Domain Wall Memories , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[10] Huazhong Yang,et al. From device to system: Cross-layer design exploration of racetrack memory , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).