An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies

An a priori hysteresis modeling methodology in partially depleted (PD) silicon-on-insulator (SOI) technologies is proposed that constitutes an essential part of an improved compact model extraction flow. By focusing on the parasitic currents, the capacitance network, the body effect, and fine-tuning the diode characteristics especially, the proposed methodology aims to closely capture the voltage and temperature dependences of hysteresis well before the full-fledged MOSFET model extraction begins. The resulting benefits, such as improved model extraction efficiency, relatively high fidelity to hardware data, and improved model accuracy, are demonstrated on a state-ofthe-art 90 nm PD SOI technology.

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