Fabrication and modeling of silicon-embedded high-Q inductors

In this paper, we report on the fabrication and modeling of a CMOS-compatible silicon-embedded high-Q integrated inductor (µH range). The fabrication process is based on DRIE, pulse-reverse super-conformal electroplating of copper and chemical–mechanical polishing. A lumped-element equivalent circuit model based on electromagnetic finite-element simulations for the determination of the element values was also developed. Inductors with different geometric design parameters were simulated to show the optimization possibility using the model. A Q-factor of over 60 (at 30–40 MHz) for a 2 µH inductor was measured, which is the highest reported in the literature for integrated inductors at such frequencies. The measurement results closely match the simulations from the lumped circuit model.