Optimization Techniques for CNT Based VLSI Interconnects - A Review

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

[1]  Jiang Hu,et al.  Boostable Repeater Design for Variation Resilience in VLSI Interconnects , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Hannu Tenhunen,et al.  Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects , 2011, IET Circuits Devices Syst..

[3]  Yintang Yang,et al.  Performance analysis of single-walled carbon nanotube bundle interconnects for three-dimensional integration applications , 2013 .

[4]  Hannu Tenhunen,et al.  Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Brajesh Kumar Kaushik,et al.  Repeater insertion in crosstalk‐aware inductively and capacitively coupled interconnects , 2011, Int. J. Circuit Theory Appl..

[6]  David Blaauw,et al.  Active shields: a new approach to shielding global wires , 2002, GLSVLSI '02.

[7]  Balwinder Raj,et al.  Temperature-Dependent Modeling and Performance Evaluation of Multi-Walled CNT and Single-Walled CNT as Global Interconnects , 2015, Journal of Electronic Materials.

[8]  Nasser Masoumi,et al.  Efficient inclusive analytical model for delay estimation of multi-walled carbon nanotube interconnects , 2012, IET Circuits Devices Syst..

[9]  Ramalingam Sridhar,et al.  Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  K. Banerjee,et al.  On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects , 2009, IEEE Transactions on Nanotechnology.

[11]  Fei Yuan,et al.  An improved RC model for VLSI interconnects with applications to buffer insertion , 2014 .

[12]  Weiping Shi,et al.  A fast algorithm for optimal buffer insertion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Mathias Beike,et al.  Digital Integrated Circuits A Design Perspective , 2016 .

[14]  Shiyan Hu,et al.  Buffering Carbon Nanotube Interconnects Considering Inductive Effects , 2016, J. Circuits Syst. Comput..

[15]  V. Sulochana Verma,et al.  Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing , 2012, ACITY.

[16]  Amirreza Alizadeh,et al.  On Temperature Dependency of Delay for Local,Intermediate, and Repeater Inserted Global Copper Interconnects , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Yingchieh Ho,et al.  Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[18]  B. Venkataramani,et al.  Design of a novel differential on-chip wave-pipelined serial interconnect with surfing , 2013, Microprocess. Microsystems.

[19]  Mayank Kumar Rai,et al.  Temperature dependant crosstalk analysis in coupled single‐walled carbon nanotube (SWCNT) bundle interconnects , 2015, Int. J. Circuit Theory Appl..

[20]  Reza Sarvari,et al.  New Approach to VLSI Buffer Modeling, Considering Overshooting Effect , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Eby G. Friedman,et al.  Crosstalk modeling for coupled RLC interconnects with application to shield insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Dipen Patel,et al.  Carbon nanotube bundle interconnect: Performance evaluation, optimum repeater size and insertion for global wire , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[23]  Nasser Masoumi,et al.  Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires , 2012, Microelectron. J..

[24]  S. D. Pable,et al.  Interconnect Design for Subthreshold Circuits , 2012, IEEE Transactions on Nanotechnology.

[25]  Renatas Jakushokas,et al.  Resource Based Optimization for Simultaneous Shield and Repeater Insertion , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Gaofeng Wang,et al.  Estimation of Time Delay and Repeater Insertion in Multiwall Carbon Nanotube Interconnects , 2011, IEEE Transactions on Electron Devices.

[27]  Hai Lin,et al.  Modeling of Crosstalk Effects in Multiwall Carbon Nanotube Interconnects , 2012, IEEE Transactions on Electromagnetic Compatibility.

[28]  S. D. Pable,et al.  Interconnect optimization to enhance the performance of subthreshold circuits , 2013, Microelectron. J..

[29]  Pasquale Cocchini A methodology for optimal repeater insertion in pipelined interconnects , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Muhammet Mustafa Ozdal,et al.  Algorithms for Maze Routing With Exact Matching Constraints , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Brajesh Kumar Kaushik,et al.  Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect , 2015, J. Circuits Syst. Comput..

[32]  Jaemin Lee,et al.  On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor , 2015, IEICE Electron. Express.

[33]  Malgorzata Marek-Sadowska,et al.  A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Nasser Masoumi,et al.  A thorough investigation into active and passive shielding methods for nano-VLSI interconnects against EMI and crosstalk , 2015 .

[35]  P. S. Mallick,et al.  Role of Semiconducting Carbon Nanotubes in Crosstalk Reduction of CNT Interconnects , 2013, IEEE Transactions on Nanotechnology.

[36]  A. Naeemi,et al.  Cu Interconnect Limitations and Opportunities for SWNT Interconnects at the End of the Roadmap , 2013, IEEE Transactions on Electron Devices.

[37]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2004, Integr..

[38]  Emre Salman,et al.  Shielding Methodologies in the Presence of Power/Ground Noise , 2011, IEEE Trans. Very Large Scale Integr. Syst..

[39]  Hai Zhou,et al.  Simultaneous routing and buffer insertion with restrictions onbuffer locations , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[40]  C. Xu,et al.  Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects , 2009, IEEE Transactions on Electron Devices.

[41]  Mohd. Hasan,et al.  Analysis of CNT bundle and its comparison with copper interconnect for CMOS and CNFET drivers , 2009 .

[42]  S. D. Pable,et al.  High speed interconnect through device optimization for subthreshold FPGA , 2011, Microelectron. J..

[43]  Manisha Pattanaik,et al.  VLSI scaling methods and low power CMOS buffer circuit , 2013 .

[44]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[45]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[46]  Gaofeng Wang,et al.  Repeater insertion for carbon nanotube interconnects , 2014 .

[47]  Kaustav Banerjee,et al.  A power-optimal repeater insertion methodology for global interconnects in nanometer designs , 2002 .

[48]  Partha Sharathi Mallick,et al.  Transient analysis of mixed carbon nanotube bundle interconnects , 2011 .

[49]  Wayne P. Burleson,et al.  Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[50]  A Naeemi,et al.  Ultralow-Power Single-Wall Carbon Nanotube Interconnects for Subthreshold Circuits , 2011, IEEE Transactions on Nanotechnology.

[51]  Rajeevan Chandel,et al.  Mixed carbon nanotube bundle: Capacitance analysis and comparison with copper interconnect , 2011, 2011 International Conference on Emerging Trends in Electrical and Computer Technology.

[52]  Mohamad Sawan,et al.  On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[53]  Partha Sharathi Mallick,et al.  Inter-CNT capacitance in mixed CNT bundle interconnects for VLSI circuits , 2012 .

[54]  R. K. Sharma,et al.  Impact of driver size and interwire parasitics on crosstalk noise and delay , 2014 .

[55]  Partha Sharathi Mallick,et al.  Towards realisation of mixed carbon nanotube bundles as VLSI interconnects: A review , 2012, Nano Commun. Networks.

[56]  Amirreza Alizadeh,et al.  Temperature-Dependent Comparison Between Delay of CNT and Copper Interconnects , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.