ENERGY CONSUMPTION REDUCTION MECHANISM BY TUNING CACHE CONFIGURATION USING NIOS II PROCESSOR

The memory hierarchy of an embedded system can consume up to 50% of microprocessor system power [1]. This paper proposes: (i) a design flow to estimate energy consumption and performance using an SoC system based on FPGA, and (ii) an automated architecture exploration mechanism based on parameter variation of a memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with g% of the design space, an energy consumption reduction of about 270/0 has been achieved, as well as an increase of 10% in the performance of the application.