PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator

This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a -47 dB PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.

[1]  Gyu-Hyeong Cho,et al.  Load-Independent Control of Switching DC-DC Converters With Freewheeling Current Feedback , 2008, IEEE J. Solid State Circuits.

[2]  Weifeng Sun,et al.  A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control , 2011, 2011 9th IEEE International Conference on ASIC.

[3]  Pengfei Li,et al.  A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization , 2011, IEEE Journal of Solid-State Circuits.

[4]  Gabriel A. Rincón-Mora,et al.  High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Chul Kim,et al.  A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[6]  Chen Zheng,et al.  A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[7]  Kae Wong,et al.  A 150mA Low Noise, High PSRR Low-Dropout Linear Regulator in 0.13μm Technology for RF SoC Applications , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[8]  Willy Sansen.  Amplifiers, Source followers & Cascodes , 2006 .

[9]  Wolfgang Pribyl,et al.  A digitally controlled linear voltage regulator in a 65nm CMOS process , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[10]  Yi-Gyeong Kim,et al.  A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[11]  Ke-Horng Chen,et al.  A 65nm sub-1V multi-stage low-dropout (LDO) regulator design for SoC systems , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[12]  Wolfgang Pribyl,et al.  Fast transient response capacitor-free linear voltage regulator in 65nm CMOS , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[13]  Philip K. T. Mok,et al.  Wide-Loading-Range Fully Integrated LDR With a Power-Supply Ripple Injection Filter , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Gabriel A. Rincón-Mora,et al.  A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[15]  Pak Kwong Chan,et al.  A 0.9-/spl mu/A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.